With the rapid advancement of VLSI technology, there is an ever-increasing demand for higher performance and more functionality in integrated circuits. However, this comes at the cost of higher power consumption. The power dissipation of VLSI chips has become a major concern, as it leads to increased chip temperatures, thermal stresses, and cooling costs. It also limits battery life in portable devices and the density of integration. To address these issues, power efficiency has become one of the primary design goals along with performance and area. This article discusses some of the emerging trends in vlsi design that aim to improve power efficiency without compromising on other metrics.
Low-Power Design Techniques
At the circuit level, there are several techniques that designers employ to reduce power consumption:
- Multi-Threshold CMOS (MTCMOS) – Using multiple threshold voltages (Vth) for transistors allows designers to operate some transistors in the sub-threshold region for reduced leakage. High-Vth transistors are used for always-on circuits like retention latches, while low-Vth transistors are used in the critical paths.
- Power Gating – It involves adding sleep transistors between the power supply and functional blocks. When a block is idle, the sleep transistor is turned off, cutting off power to that block. This significantly reduces leakage power. Finer-grained power gating with multiple sleep transistors provides better power savings.
- Variable Supply Voltage – The supply voltage can be dynamically varied depending on workload and performance requirements. Lowering the voltage reduces both dynamic and static power consumption quadratically. However, it also lowers the maximum operating frequency.
- Clock Gating – It disables the clock signal to idle modules, avoiding unnecessary signal transitions and thereby reducing dynamic power. Fine-grained clock gating with multiple clock domains helps improve power savings.
- Body Biasing – Applying a reverse bias to the substrate reduces Vth, allowing higher performance. Forward biasing increases Vth to reduce leakage for low-power modes. Adaptive body biasing provides dynamic control.
At the architectural level, techniques like DVFS (Dynamic Voltage and Frequency Scaling), power-aware scheduling, and activity migration help optimize power. Emerging trends focus on making these techniques more fine-grained and adaptive.
Emerging Low-Power Design Trends
Some emerging trends in low-power vlsi circuit design include:
- Near-Threshold Computing
Near-threshold computing refers to operating circuits at a supply voltage just above the transistor threshold voltage. This leads to significant power savings as power is quadratically proportional to voltage. Near-threshold voltage is around 600mV compared to the conventional super-threshold voltage of 1V and above.
However, at such low voltages, circuit delays increase exponentially. So proper optimization of device sizing, circuits and system architecture is required to achieve robust functionality without major performance loss. Researchers are working on co-designing transistors, logic gates, functional blocks and overall system architecture suited for near-threshold voltage ranges. This involves techniques like increasing transistor widths, adding buffers, redesigning logic styles etc.
The co-design approach explores synergistic optimization across different levels to realize the benefits of ultra-low voltage operation while maintaining reasonable performance. This can potentially lead to major improvements in power efficiency of integrated circuits.
- 3D Integration and Monolithic 3D ICs
3D integration involves stacking multiple silicon dies vertically using a technique called Through-Silicon Vias (TSVs). TSVs are vertical interconnects drilled through the silicon die that allow connecting different layers in three dimensions. This reduces the length of interconnect wiring compared to conventional 2D layouts. Shorter wire lengths lead to lower resistance and capacitance, thereby reducing the dynamic power consumed during signal transitions.
Monolithic 3D ICs take this a step further by sequentially fabricating multiple active device layers on the same silicon wafer. This makes it possible to have fine-grained power domains within each layer and also explore novel 3D circuit styles that can further improve power efficiency. However, stacking multiple layers also increases power density and thermal issues need to be carefully addressed in 3D integrated circuit design.
- Process Variation Resilience
As transistor feature sizes shrink with technology nodes, manufacturing process variations that arise due to small fluctuations in dopant concentrations, gate oxide thicknesses etc. have a significant impact on power, performance and reliability of chips. Different parts of the same die may end up having different threshold voltages and leakage/power characteristics due to these process variations.
Design techniques like variation-aware optimization during synthesis/placement, adaptive body biasing to control threshold voltage dynamically and variation-tolerant circuit styles help improve the resilience of chip design against the effects of process variations. They enable reliable operation at low voltages. Online monitoring of process parameters using on-chip sensors during actual chip operation and compensating for any deviations through techniques like adaptive body biasing further aid in low-power operation under the impact of inevitable process variations.
- Neuromorphic Computing
Neuromorphic architectures inspired by the brain’s low-power operation have emerged as an alternative computing paradigm. Event-driven and asynchronous logic styles, along with non-von Neumann architectures provide new opportunities for ultra-low-power design. Research is ongoing in the co-design of neuromorphic hardware and algorithms.
- Approximate Computing
Approximate computing techniques relax precision/accuracy for significant power savings by exploiting the error-resilience of many applications like multimedia, machine learning, etc. Approximation can be applied at various levels – circuit, architecture, system software/hardware. However, it requires a thorough understanding of the impact on quality and managing the trade-off between power and accuracy.
- Integrated Voltage Regulators
On-chip voltage regulation provides tighter control over supply voltage and faster DVFS compared to off-chip regulators. Monolithic integration of regulators enables fine-grained per-block or even per-IP voltage domains for improved power management. Efficient regulation under process variations is an active research area.
- Energy-Aware Computing Systems
At the system-level, energy-aware resource management across hardware and software layers helps optimize the overall energy efficiency. Co-design of applications, architecture, OS, and runtime is required to achieve the best energy-delay product. On-chip sensors and machine learning enable self-aware systems with adaptive optimization.
Conclusion
With the end of Moore’s Law in sight and power becoming a primary constraint, low-power design in embedded system solution will continue gaining importance. The emerging trends discussed aim to overcome the limitations of conventional techniques and push the boundaries of power efficiency. Future research directions include 3D/monolithic integration, near-threshold design, neuromorphic approaches, and self-aware energy optimization across all system layers. Power-efficient computing will be crucial to enable continued technology scaling and new application domains.
